4 facts filed under Host interfaces and protocols: 2 read in the original source and 2 reported by a second source. Each was checked against the source’s own words, so its figures appear there, and each names where it comes from. The idea is taught in Part 1, Standards & Interfaces.
Primary sources
CXL dynamically multiplexes three protocols: CXL.io (based on PCIe), CXL.cache for caching and CXL.memory for memory semantics, keeping one coherent memory space between the host CPU and memory on the attached device.
SMART’s CXA-8F2W-D4 is a CXL 2.0 Type 3 add-in card that connects over PCIe Gen5 x16 and translates CXL.mem transactions into DDR4 commands, so reused DDR4 modules show up as extra host memory; it was shown as a mechanical sample, not a running system.
Secondary sources
Type 3 memory expanders speak CXL.io plus CXL.mem; CXL.cache is used when a device caches host memory.
A CXL Type 3 device supports only CXL.io and CXL.mem and targets memory capacity and bandwidth expansion; a Type 2 device supports CXL.io, CXL.cache and CXL.mem.
Sources
Primary is the original paper, standard or datasheet. Secondary is a review, a vendor summary or a news report. Measured is my own test data.
Show all 4 sources, 2 primary
- SecondaryIntroduction to CXL 2.0 Memory (LP2146)Lenovo Press
- PrimaryCompute Express Link 3.0 White PaperCXL Consortium, 2022
- SecondaryIntroduction to Compute Express Link (CXL) Memory ModulesSMART Modular Technologies, 2023
- PrimaryCXL Gives DDR4 a Second Life: Penguin Solutions Demonstrates Memory Reuse at SC26CXL Consortium blog, 2026