The Planar Scaling Wall

Secondary sources

• Micron’s 2013 16 nm cell was about 0.0013 um2, about 5.1F2, above the 4F2 ideal.

  Published resultCharge-Trapping Non-Volatile Memories

• About 500 electrons on a NAND floating gate at the 45 nm node (about 1,000 for NOR).

  Published resultCharge-Trapping Non-Volatile Memories

• Frozen planar parameters: tunnel oxide near 7 nm, interpoly dielectric near 10 nm, MLC operating voltage near 25 V, wordline-to-wordline field above 10 MV/cm.

  Published resultFigures: 7 nm; 10 nm; 25 V; 10 MV/cmCharge-Trapping Non-Volatile Memories

• Planar NAND scaling reached the 15nm node, after which the conventional scaling path could no longer be followed.

  Published resultReliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

• The self-aligned STI cell reached a cell size of 0.31um2 at a 0.25um design rule.

  Published resultNand Flash Memory Devices

• The 2013 Micron 16nm NAND cell measured about 0.0013um2 (printed as 1.3 x 10^-3 um2; the minus sign is lost in extraction), about 5.1F2.

  Published resultCharge-Trapping Non-Volatile Memories

• At the 45nm technology node, NOR cells need 1,000 electrons and NAND cells 500 electrons on the floating gate.

  Published resultCharge-Trapping Non-Volatile Memories

• Frozen planar parameters: tunnel oxide stuck near 7nm, interpoly dielectric near 10nm, MLC operating voltage near 25V.

  Published resultFigures: 7nm; 10nm; 25VCharge-Trapping Non-Volatile Memories

• The wordline-to-wordline field in planar NAND is trending to above 10MV/cm.

  Published resultFigures: >10MV/cmCharge-Trapping Non-Volatile Memories

• In a sub-20nm self-aligned STI wrap cell, the aspect ratio of the stacked gate and the control-gate fill becomes more than 10.

  Published resultFigures: >10Nand Flash Memory Devices

• NAND cell area was 1.13 um2 for the conventional LOCOS cell at the 0.4 um rule and 0.67 um2 for the SA-STI cell at the 0.35 um rule.

  Published resultFigures: 1.13; 0.67 um2Nand Flash Memory Devices

• The NAND flash cell has been scaled down over 20 years, from above 0.7 um to 1X nm, at about 1.5 year per generation (20 years over 13 generations).

  Published resultFigures: 1.5 yrNand Flash Memory Devices

• For 3D NAND the physical cell size has been increased by more than 20 times compared to the sub-20 nm 2D NAND cell, and the number of electrons for a 100 mV Vt shift by more than eight times.

  Published resultFigures: 20x; 8xSemiconductor Memories and Systems