4 facts filed under 3D structure and process: 1 read in the original source and 3 reported by a second source. Each was checked against the source’s own words, so its figures appear there, and each names where it comes from. The idea is taught in Part 4, 3D NAND Stacking.
Primary sources
Samsung followed with a double-stacked 4Gb multi-level NAND flash, a 45nm 4-Gigabit three-dimensional double-stacked part (Park, JSSC 2009).
Secondary sources
Each stacked-planar layer needed about 3 critical lithography modules so cost scaled with layers; punch-and-plug keeps critical lithography constant.
Each layer of a stacked-planar 3D NAND needs at least 3 critical process modules (bitline, wordline, contact), so cost multiplies with the number of layers.
In BiCS the number of critical lithography steps stays constant as layers are added, because the whole stack of control gates is punched through in one lithography step.
Related concepts
Sources
Primary is the original paper, standard or datasheet. Secondary is a review, a vendor summary or a news report. Measured is my own test data.
Show all 4 sources, 3 primary
- Secondary3D Flash MemoriesSpringer, 2016
- PrimaryThree Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node2006 International Electron Devices Meeting, 2006
- PrimaryA Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory2006 International Electron Devices Meeting, 2006
- PrimaryA Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line StructureIEEE Journal of Solid-State Circuits, 2009