Process Variation in Tall Stacks

Samsung’s V-NAND paper (Kang et al., JSSC) presents a reverse read scheme and a variable-pulse scheme to cope with nonuniform wordline characteristics.

Published result256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers

Hung et al. (IEEE JSSC, volume 50, 2015) titled their work Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations.

Published resultLayer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations

In 3D NAND the error rate of each layer in the stack differs widely because of layer-to-layer process variation.

Published resultArchitectural Techniques for Improving NAND Flash Memory Reliability

The hole interrupts the wordline plate, so wordline resistance and program transients differ by layer.

Published result3D Flash Memories

Taper: the top cell is larger and the smallest bottom cell sets the minimum; workable layer pitch near 40 nm with Lg = Lspace = 20 nm.

Published resultFigures: 40 nm pitch; 20/20 nm3D Flash Memories

A layer pitch of 40nm, with a gate length and spacing of 20nm each, is achievable in 3D NAND in terms of electrical characteristics.

Published resultFigures: 40nm pitch; 20/20nm3D Flash Memories

Taper: the cell at the top of the stack is always larger than the cell at the bottom, so once the bottom cell reaches the minimum size the area cannot shrink further.

Published result3D Flash Memories

The channel hole is a physical barrier to charge flow along the wordline, so a variation of hole size varies the parasitic resistance and the voltage transient depends on the layer.

Published result3D Flash Memories