10 facts filed under 3D structure and process: all 10 are reported by a second source. Each was checked against the source’s own words, so its figures appear there, and each names where it comes from. The idea is taught in Part 4, 3D NAND Stacking.
Secondary sources
Trim-and-etch staircase: one mask can in theory make many steps, resist trim limits it, and staircase area grows in proportion to layer count.
MiLC binary-sum staircase for vertical-gate 3D NAND: 8 layers need 3 masks instead of 8, and doubling the layers adds one mask.
Routing 16 layers within the pitch of two pillar rows is a different job than across eight rows.
Program and read disturb spread along the plate in proportion to pillars per control-gate plate; slits trade density against disturb and block size.
Trim-and-etch staircase: one lithographic mask could in theory make all the steps, but control gets difficult as layers grow, and the staircase area grows linearly with layer count.
MiLC staircase for vertical-gate 3D NAND: for 8 layers, a superimposition of three masks opens each polysilicon layer.
With the MiLC staircase, doubling the number of layers and contacts takes one extra mask.
Connecting 16 layers within the pitch of 2 rows of pillars is a different job from connecting them within the pitch of 8 rows.
Disturb is proportional to the number of pillars per control-gate layer, so slits that cut the layer into smaller blocks limit the spread of program and read disturb.
The downside of array slits is their cost in silicon area, because the matrix becomes wider along the Y direction.
Sources
Primary is the original paper, standard or datasheet. Secondary is a review, a vendor summary or a news report. Measured is my own test data.
Show all 1 sources
- Secondary3D Flash MemoriesSpringer, 2016