Week endingFriday, November 13, 2026Covers November 7 to November 13, 2026 · 15 items
Makers spent the week treating flash as more than a disk. AMD describes software that tiers cold DRAM pages onto NVMe flash, Seagate ships an external hybrid that expects you to install the SSD, and Kioxia with Dell show high capacity SSDs filling a dense object storage rack.
CXL still leads the standards and demos track, with Intel and Netlist posts and a SNIA SC26 preview. Research keeps asking where HBM controllers should live and how high bandwidth flash behaves next to a GPU. YMTC's tool localization plans and PC memory buying caution round out the market picture.
Sandisk introduced its iNAND CL EM181 embedded flash drive for connected devices. It keeps the established e.MMC interface while moving to newer NAND, aiming to reduce host changes and qualification work for products with long lifecycles.
Sandisk ·
SK hynix says its LPDDR5X memory and development process earned industrial functional safety certification, alongside certification of its automotive cybersecurity management process. It targets uses including robotics and smart factories.
SK hynix ·
Writing on the CXL Consortium's site, Intel describes a demo on a preproduction Xeon processor. Its Flat Memory Mode manages data between local DRAM and CXL expansion memory in hardware, aiming to keep frequently accessed data close to the processor.
Intel via CXL Consortium ·
Kioxia says its LC9 Series enterprise SSDs, built on BiCS FLASH QLC, are used in a Dell ObjectScale build on PowerEdge servers. The companies present it as a dense all flash object store for AI and data lake workloads, with less floor space and cooling than hard drive heavy designs at the same capacity.
Seagate introduced FireCuda Forge, an external drive that pairs a high capacity hard drive with a user installed M.2 NVMe SSD. Its Alkemi software caches frequently used files on the SSD while the hard drive holds the larger library, and the unit will not run without a compatible SSD installed.
AMD presents MEXT as a software only product that moves cold DRAM pages to NVMe flash and uses prediction to bring likely pages back before they are needed. The pitch is usable memory capacity without buying as much DRAM, with no application changes required.
Netlist plans to demonstrate CXL memory prototypes at SC26. The designs pair DRAM with NAND for tiering, back up DRAM during power loss, or make existing DDR4 available as expanded host memory. These are proof of concept designs.
SNIA plans demonstrations of CXL attached MRAM and the recently approved SDXI specification at its SC26 pavilion. The program also covers SSD cooling and storage management. Its announcement describes planned demonstrations, rather than new shipping products.
TrendForce says weak PC sales and rising inventories are prompting some manufacturers to reassess memory purchases. It expects PC DRAM and client SSD contract prices to keep rising, with increases moderating as buyers resist further cost pressure.
Reported by TrendForce; the company has not confirmed it yet.
DigiTimes reports that YMTC wants Chinese made equipment to cover most of the tool list at a new NAND fab, while still depending on foreign tools for advanced process steps. The story is a secondary report on localization plans, not a YMTC release.
Reported by DigiTimes; the company has not confirmed it yet.
Researchers simulate dividing memory controller work between a processor and the logic chip beneath an HBM stack. The study weighs host chip area against link delay, power, and temperature. It evaluates modeled designs rather than measured production hardware.
arXiv ·
A simulation study asks whether flash near a GPU can hold model weights and reduce the GPUs needed to serve an AI model. The authors find that hardware savings and throughput gains occur in different scenarios, with the case depending on workload and flash cost.
arXiv ·
SlipStream studies High Bandwidth Flash as a denser stand in for HBM on GPU systems. The authors model the long flash read delay and propose techniques to cut SRAM overhead and keep inference from stalling on flash fetches. Results come from simulation, not shipping hardware.
arXiv ·