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    Back to the Parallelism Lab

    Sources

    Every number in the lab’s presets comes from the Eyes on Flash dataset (src/data/flash-db in the site repository), where each value carries a public source. The dbId of a preset is the id of its record there. The site’s tests fail if a preset drifts from its record.

    NAND dies

    4th-gen V-NAND 512Gb TLC (64 WL)

    samsung-4th-gen-v-nand-512gb-tlc-64-wl

    • capacity_gbit: 512. A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory (IEEE JSSC, 2018), doi:10.1109/JSSC.2017.2731813, p. 6 of the digest or PDF
    • planes: 2. A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory (IEEE JSSC, 2018), doi:10.1109/JSSC.2017.2731813, p. 7 of the digest or PDF
    • page_kb: 16. A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory (IEEE JSSC, 2018), doi:10.1109/JSSC.2017.2731813, p. 6 of the digest or PDF
    • io_mts: 1000. A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory (IEEE JSSC, 2018), doi:10.1109/JSSC.2017.2731813, p. 6 of the digest or PDF. The lab preset runs this die at 800 MT/s (the product rate, from the dataset’s io_product_mts, Samsung FMS 2016 release) because the lab uses the lower of the die and controller bus rates, min(die, controller).
    • tprog_us: 700. A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory (IEEE JSSC, 2018), doi:10.1109/JSSC.2017.2731813, p. 6 of the digest or PDF
    • program_mbs: 51. A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology (IEEE JSSC, 2020), doi:10.1109/JSSC.2019.2941758, p. 2, Fig. 3 comparison table, column [6] (Samsung 2017, 64 layers, 512Gb: 51MB/s at tPROG 700us). A survey figure printed by Kioxia authors; Samsung’s own paper prints only tPROG. An earlier 57MB/s was Toshiba/Kioxia’s 96-layer die, not this one

    6th-gen V-NAND 512Gb TLC

    samsung-6th-gen-v-nand-512gb-tlc

    • capacity_gbit: 512. 13.4 A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface (ISSCC, 2019), doi:10.1109/ISSCC.2019.8662493, p. 2 of the digest or PDF
    • planes: 2. 13.4 A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface (ISSCC, 2019), doi:10.1109/ISSCC.2019.8662493, p. 1 of the digest or PDF
    • page_kb: 16. 13.4 A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface (ISSCC, 2019), doi:10.1109/ISSCC.2019.8662493, p. 2 of the digest or PDF
    • io_mts: 1200. 13.4 A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface (ISSCC, 2019), doi:10.1109/ISSCC.2019.8662493, p. 2 of the digest or PDF
    • program_mbs: 82. 13.4 A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface (ISSCC, 2019), doi:10.1109/ISSCC.2019.8662493, p. 2 of the digest or PDF

    7th-gen V-NAND 512Gb TLC (CoP)

    samsung-7th-gen-v-nand-512gb-tlc-cop

    • capacity_gbit: 512. 30.3 A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface (ISSCC, 2021), doi:10.1109/ISSCC42613.2021.9366054, p. 3 of the digest or PDF
    • planes: 4. 30.3 A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface (ISSCC, 2021), doi:10.1109/ISSCC42613.2021.9366054, p. 1 of the digest or PDF
    • page_kb: 16. 30.3 A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface (ISSCC, 2021), doi:10.1109/ISSCC42613.2021.9366054, p. 3 of the digest or PDF
    • io_mts: 2000. 30.3 A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface (ISSCC, 2021), doi:10.1109/ISSCC42613.2021.9366054, p. 3 of the digest or PDF
    • program_mbs: 184. 30.3 A 512Gb 3b/Cell 7th-Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface (ISSCC, 2021), doi:10.1109/ISSCC42613.2021.9366054, p. 3 of the digest or PDF

    ISSCC 2019 512Gb TLC 128 WL layers, CuA, 4-plane

    western-digital-kioxia-toshiba-memory-isscc-2019-512gb-tlc-128-wl-layers-cua-4-plane

    • capacity_gbit: 512. 13.5 A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology (ISSCC, 2019), doi:10.1109/ISSCC.2019.8662445, p. 2 of the digest or PDF
    • planes: 4. 13.5 A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology (ISSCC, 2019), doi:10.1109/ISSCC.2019.8662445, p. 2 of the digest or PDF
    • page_kb: 16. 13.5 A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology (ISSCC, 2019), doi:10.1109/ISSCC.2019.8662445, p. 2 of the digest or PDF
    • io_mts: 1066. 13.5 A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology (ISSCC, 2019), doi:10.1109/ISSCC.2019.8662445, p. 2 of the digest or PDF
    • program_mbs: 132. 13.5 A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology (ISSCC, 2019), doi:10.1109/ISSCC.2019.8662445, p. 2 of the digest or PDF

    BiCS6 1Tb QLC (162 WL layers, WD/Kioxia)

    kioxia-bics6-1tb-qlc-162-wl-layers-wd-kioxia

    • capacity_gbit: 1024. A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface (ISSCC, 2022), doi:10.1109/ISSCC42614.2022.9731110, p. 2 of the digest or PDF
    • planes: 4. A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface (ISSCC, 2022), doi:10.1109/ISSCC42614.2022.9731110, p. 2 of the digest or PDF
    • io_mts: 2400. A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface (ISSCC, 2022), doi:10.1109/ISSCC42614.2022.9731110, p. 2 of the digest or PDF
    • program_mbs: 60. A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface (ISSCC, 2022), doi:10.1109/ISSCC42614.2022.9731110, p. 2 of the digest or PDF

    176L TLC 512Gb (4D PUC)

    sk-hynix-176l-tlc-512gb-4d-puc

    • capacity_gbit: 512. 30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture (ISSCC, 2021), doi:10.1109/ISSCC42613.2021.9365809, p. 26 of the digest or PDF
    • planes: 4. 30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture (ISSCC, 2021), doi:10.1109/ISSCC42613.2021.9365809, p. 26 of the digest or PDF
    • page_kb: 16. 30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture (ISSCC, 2021), doi:10.1109/ISSCC42613.2021.9365809, p. 16 of the digest or PDF
    • io_mts: 1600. 30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture (ISSCC, 2021), doi:10.1109/ISSCC42613.2021.9365809, p. 26 of the digest or PDF
    • program_mbs: 168. 30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture (ISSCC, 2021), doi:10.1109/ISSCC42613.2021.9365809, p. 26 of the digest or PDF

    96L QLC 1Tb (PUC)

    sk-hynix-96l-qlc-1tb-puc

    • capacity_gbit: 1024. 13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique (ISSCC, 2020), doi:10.1109/ISSCC19947.2020.9063117, p. 2 of the digest or PDF
    • planes: 4. 13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique (ISSCC, 2020), doi:10.1109/ISSCC19947.2020.9063117, p. 1 of the digest or PDF
    • page_kb: 16. 13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique (ISSCC, 2020), doi:10.1109/ISSCC19947.2020.9063117, p. 1 of the digest or PDF
    • io_mts: 800. 13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique (ISSCC, 2020), doi:10.1109/ISSCC19947.2020.9063117, p. 2 of the digest or PDF
    • tprog_us: 2150. 13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique (ISSCC, 2020), doi:10.1109/ISSCC19947.2020.9063117, p. 1 of the digest or PDF
    • program_mbs: 30. 13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique (ISSCC, 2020), doi:10.1109/ISSCC19947.2020.9063117, p. 2 of the digest or PDF

    144L FG 1Tb QLC

    intel-144l-fg-1tb-qlc

    • capacity_gbit: 1024. 30.2 A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm2 Bit Density (ISSCC, 2021), doi:10.1109/ISSCC42613.2021.9365777, p. 23 of the digest or PDF
    • planes: 4. 30.2 A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm2 Bit Density (ISSCC, 2021), doi:10.1109/ISSCC42613.2021.9365777, p. 23 of the digest or PDF
    • io_mts: 1200. 30.2 A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm2 Bit Density (ISSCC, 2021), doi:10.1109/ISSCC42613.2021.9365777, p. 23 of the digest or PDF
    • tprog_us: 1630. 30.2 A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm2 Bit Density (ISSCC, 2021), doi:10.1109/ISSCC42613.2021.9365777, p. 23 of the digest or PDF
    • program_mbs: 40. 30.2 A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm2 Bit Density (ISSCC, 2021), doi:10.1109/ISSCC42613.2021.9365777, p. 24 of the digest or PDF

    XL-FLASH G1 128Gb SLC (96 WL layers)

    kioxia-xl-flash-g1-128gb-slc-96-wl-layers

    • capacity_gbit: 128. A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 us and tR = 4 us (IEEE JSSC, 2021), doi:10.1109/JSSC.2020.3028393, p. 2 of the digest or PDF
    • planes: 16. A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 us and tR = 4 us (IEEE JSSC, 2021), doi:10.1109/JSSC.2020.3028393, p. 2 of the digest or PDF
    • page_kb: 4. A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 us and tR = 4 us (IEEE JSSC, 2021), doi:10.1109/JSSC.2020.3028393, p. 2 of the digest or PDF
    • io_mts: 800. A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 us and tR = 4 us (IEEE JSSC, 2021), doi:10.1109/JSSC.2020.3028393, p. 2 of the digest or PDF
    • tprog_us: 75. A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 us and tR = 4 us (IEEE JSSC, 2021), doi:10.1109/JSSC.2020.3028393, p. 2 of the digest or PDF

    Controllers

    Silicon Motion SM2263XT

    silicon-motion-sm2263xt

    Silicon Motion SM2263EN

    silicon-motion-sm2263en

    Silicon Motion SM2262EN

    silicon-motion-sm2262en

    Silicon Motion SM2267XT

    silicon-motion-sm2267xt

    Silicon Motion SM2267

    silicon-motion-sm2267

    Not from the dataset

    • PCIe bandwidth. Per lane, after line coding: Gen 1 250 MB/s, Gen 2 500 MB/s (8b/10b), Gen 3 985 MB/s, Gen 4 1,969 MB/s, Gen 5 3,938 MB/s (128b/130b). These follow from the PCI Express Base Specification transfer rates (PCI-SIG): 2.5, 5, 8, 16 and 32 GT/s per lane.

    • Bus width. The lab takes a NAND bus to be one byte wide (x8), so N MT/s moves N MB/s per channel. ONFI 5.2 requires an 8-bit bus for devices using the NV-DDR, NV-DDR2, NV-DDR3 or NV-LPDDR4 data interface.

    • Die count. Capacity in GB (decimal, as marketed) times 8, divided by the die capacity in Gbit, rounded up. Over-provisioning is ignored.

    • Program throughput from tPROG. Where a paper prints only tPROG, the throughput is planes x page size / tPROG, in bytes per microsecond. test/parallelism-model.test.mjs checks that this reproduces the throughput printed by the SK hynix 96-layer QLC paper (printed together with its tPROG) to within 3 percent.

    • Schedule. The bus timeline is a model. Each die has a one-page cache register, so the next page can cross the bus while the last programs, and the bus serves whichever die is ready first.

    • Read speed. A multi-plane read returns a page from every plane each tR, so one die reads at planes x page size / tR in bytes per microsecond, using the page read time (tr_us) the dataset records for each die. The bus and host ceilings are the same as for writes. It is an upper bound: no cache-read pipelining and no decode time inside a plain read. Read-retry is the next entry. test/parallelism-read.test.mjs checks the formula and that every die preset carries a tR.

    • Commands in flight. A queue of Q commands landing on N dies at random keeps N x (1 - (1 - 1/N)^Q) dies busy (the expected number of distinct dies hit). This is arithmetic, not a measurement, and it assumes no write cache: a drive that acknowledges from DRAM keeps more dies busy than the queue depth suggests. test/parallelism-read.test.mjs checks the formula.

    • PCIe Gen 6 and packet framing. Gen 6 is 64 GT/s with PAM4 and flit encoding (PCI-SIG, “PCI-SIG Releases PCIe 6.0 Specification”, press release, 11 January 2022): 8 GB/s a lane per direction, 32 GB/s for an x4 link, before framing. The lab does not take flit overhead out of that figure. The packet framing menu uses payload / (payload + 20 bytes), the calculation in J. Lawley, “Understanding Performance of PCI Express Systems”, Xilinx WP350 v1.2 (2014), Table 3 (86% at 128 bytes, 92% at 256, 96% at 512). Its 20 bytes are Gen 1 to Gen 3 framing, so for later generations the factor is a teaching value.

    • Cache register off, and the classic SLC die. Program time per page without a cache register is tPROG plus the transfer, page / (tPROG + page / bus); with one, the transfer hides behind the program. The same arithmetic is in S.-C. Park et al., “Program Cache Busy Time Control Method for Reducing Peak Current Consumption of NAND Flash Memory in SSD Applications” (16 KB page, tPROG 500 microseconds, 166 MB/s: 27.3 MB/s without a cache, 32.8 with). The classic die is from Micron TN-29-19, “NAND Flash 101” (Rev. B, 4/10): a 2Gb asynchronous SLC with a 2KB page, tPROG 220 microseconds, tR 25 microseconds and 25 ns per byte, which the note says sustains 7.5 MB/s of writes. The die is not in the dataset, so it lives in REFERENCE_DIE_PRESETS.

    • 16- and 32-channel geometries. What-if controllers, not products. The 16-channel one takes its channel count and PCIe generation from the dataset record for a vendor’s 8 and 16 channel family (a 2021 press release); its other numbers, and all of the 32-channel one, are the lab’s own.

    In the model, not on the page

    The page shows the dies, the channel buses and the PCIe link. These parts of the model are not on it, and their sources are kept here.

    • Read-retry and soft decoding. The sandbox’s read mode lets a chosen share of reads fall down an error-correction ladder. Only the parity rebuild time is a published figure: Y. Cai, S. Ghose, E. F. Haratsch, Y. Luo and O. Mutlu, “Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery” (arXiv:1711.11427v2, 2018), page 56, says superpage-level parity recovery “can take around 10 ms”. The soft decode times, about 80 microseconds per level and 480 for five levels, are the lab’s model values. The lab adds the stage time to the die’s tR, so the average read is tR + share x stage time and the die keeps tR / average of its read speed. The share is the visitor’s choice. Two marks on the slider come from the same paper (page 57): a hard-decision failure rate of 1 in 10,000 codewords (0.01%) and, with four codewords per page, up to 0.04% of page reads needing soft decoding. No public source gives how many reads a real drive retries at a given age, so the lab does not say. test/parallelism-retry.test.mjs checks the arithmetic.
    • Host queue limit. Little’s law (commands in flight = throughput x latency), so throughput = depth x command size / latency. Write-through latency is the program time plus a transfer per round of program operations; write-back latency is the command size over the host link. SATA: “the device queue depth is limited to 32 outstanding entries” (Serial ATA Revision 2.6, native command queuing, section 13.5). NVMe: up to 65,535 I/O queues with up to 65,535 outstanding commands each (NVM Express 1.4). The menu lists depths from 1 to 64.
    • ECC decoder limit. Decoders x per-decoder rate, with 1,200 MB/s per decoder as a teaching value: no paper the lab has opened prints it. The lab does not model the soft-decode share that rises with wear.
    • Channel power. P = 9 x activity x f x C x V^2: the standard CMOS switching relation over eight data lines and the strobe, with f the transfer rate and an activity of 0.5 (a teaching value). Pin capacitance is the Typ High column of Table 47 in the Open NAND Flash Interface specification 4.2 (I/O pins, 1 LUN 5.7 pF, 2 LUNs 8.5, 4 LUNs 14.9, 8 LUNs 28.7; counts between rows are interpolated), and VccQ of 3.3, 1.8 or 1.2 V is from the same document’s operating conditions. The table stops at 8 dies on a data bus, so the lab gives no estimate beyond that.
    • tPROG from the program staircase. K.-D. Suh et al., “A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme”, IEEE JSSC 30(11), 1149-1156 (1995): a 40 microsecond cycle (bitline setup 8, program pulse 20, wordline discharge 4, verify 8), the program voltage stepping from 15.5 V to 20 V in 0.5 V steps, and a page typically programmed within five pulses (200 microseconds). The lab’s tPROG = pulses x (32 microseconds + verify levels x 8 microseconds) reproduces that. Verify levels per pulse above one, and the step sizes other than 0.5 V, are teaching values.

    Left out on purpose

    • Pseudo-SLC mode. No source in the dataset prints the program-time speed-up of a TLC die run as SLC, so the lab does not guess one.
    • Command and address cycles, the decode time inside a plain read, the number of reads a real drive retries, garbage collection, the SLC cache, thermal throttling and the drive’s DRAM.