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    Back to the Crosspoint Lab

    Sources

    Crosspoint Lab is a teaching model. The circuit solve is exact, but every parameter is a teaching value and nothing in the lab is device data. This file says which papers describe the ideas the lab draws, and says plainly which of them were read.

    What the lab shows, and what it rests on

    • Sneak paths and read margin in a crossbar, with line resistance and a nonlinear cell. The lab’s circuit model is the same kind of model as A. Chen, “A comprehensive crossbar array model with solutions for line resistance and nonlinear device characteristics”, IEEE Transactions on Electron Devices 60(4), 2013, doi:10.1109/ted.2013.2246791. The DOI resolves; the paper was not read for this lab, so none of its numbers is used.

    • Resistive switching memories and why they are built as crossbars. H.-S. P. Wong et al., “Metal-oxide RRAM”, Proceedings of the IEEE 100(6), 2012, doi:10.1109/jproc.2012.2190369. Resolved, not read.

    • A stackable crosspoint memory with a threshold selector (ovonic threshold switch) in each cell. D. Kau et al., “A stackable cross point phase change memory”, IEDM 2009, doi:10.1109/iedm.2009.5424263. Resolved, not read.

    • Phase-change memory: crystalline and amorphous states and how a cell switches between them. H.-S. P. Wong et al., “Phase change memory”, Proceedings of the IEEE 98(12), 2010, doi:10.1109/jproc.2010.2070050. The DOI resolves; the paper was not read for this lab. Chapter 1 names phase change only as one of two ways a cell switches.

    • Analog weighted sums computed in a resistive crossbar, and the device problems that limit their accuracy. S. Ambrogio et al., “Equivalent-accuracy accelerated neural-network training using analogue memory”, Nature 558, 2018, doi:10.1038/s41586-018-0180-5. The DOI resolves; the paper was not read for this lab, so none of its numbers is used. Act 2’s sums come from the lab’s own circuit solve.

    Chapter 1’s switching loop uses the same two resistances as the array and round set, reset and read voltages (+1.2V, -1.0V, 0.2V). Real cells switch over a spread of voltages, need a current limit while they set, and many switch gradually; the loop shows the idea, not a device. Act 2’s weights (ten levels between the two resistances), inputs (0.05V to 0.2V), stuck cell, 20% spread and fixed random seed are teaching values.

    Mechanism descriptions in the walkthrough (a selector as a threshold switch with a lower holding voltage, a transistor that conducts only on the selected row, bias schemes that hold idle lines at fractions of the read voltage) are standard and are drawn from textbook-level material. The lab’s own claims are checked by its tests against its own circuit solve, which is the only thing the page asserts as fact.

    The lab’s own numbers (teaching values, in src/lib/crosspoint-model.ts)

    Value Setting
    Low-resistance cell 10kΩ
    High-resistance cell 1MΩ
    Wire between neighboring crossings 2Ω
    Line driver 2Ω
    Read voltage 2V
    Selector turn-on threshold, holding voltage 1.5V, 1V
    Selector on resistance, off conductance 1kΩ, 1nS
    Access transistor on resistance 1kΩ

    None of these is taken from a paper. The only claims they are meant to carry are shapes: the margin falls as the array grows, holding idle lines sets idle voltages without restoring margin for bare cells, and a selector or a transistor restores it. The 4F² of a bare crossing is geometry: lines every 2F in each direction.

    Not claimed

    The deck chapter says each doubling of decks halves the area per bit and that cost per bit falls by less. The first is arithmetic. The second is a qualitative statement, not a measured one.

    Converters at the array edge (0.2.1)

    • Shafiee et al., “ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars”, ISCA 2016. doi:10.1109/isca.2016.12. States that analog-to-digital converters account for a large fraction of chip power and area in crossbar accelerators. The lab models no converters and gives no number for them.

    Programming curve, drift and converters (0.4.0)

    • Programming curve (chapter 2). The anchor values come from published programming curves for two phase-change test cells, not one: a pulse of 100 to 150 ns, a reset resistance of about 1.5MΩ, a set resistance of about 3kΩ, a reset cell starting to set above about 100µA and fully set by 150µA, melting between 400 and 450µA (the lab uses 425µA), and a full reset by about 600µA with a falling edge of 10 to 15ns. The 150 ns pulse, 150µA fully set, 400µA melting, 600µA full reset and the 10 ns falling edge (10 to 15 ns in the text) are Fig. 4.10 of the book (Redaelli, ed., Phase Change Memory, 2018, chapter 4), a figure reprinted with permission from a 2004 IEEE paper that was not read. The 100 ns pulse, 100µA set onset, 450µA melting, and the 1.5MΩ and 3kΩ resistances are from a different 180 nm prototype cell in the same text (its plot reads lower than those two text values). The lab’s 425µA is the midpoint of 400 and 450 and belongs to neither cell. Treat all of them as one illustrative cell. The straight joins between anchors on a log axis are the lab’s own drawing.
    • Threshold switching. That a glassy cell must switch to a conducting state before a pulse can heat it enough is the finding of A. Pirovano et al., “Electronic switching in phase-change memories”, IEEE Transactions on Electron Devices 51(3), 2004, pp. 452-459, doi:10.1109/ted.2003.823243. The DOI resolves; the paper was not read, and chapter 2 states the idea in words and gives no number from it.
    • Drift. Resistance of the reset state rising as R = R0 (t/t0)^nu with nu near 0.1, and the set state not drifting: A. Pirovano et al., IEEE TED 51(5), 2004, pp. 714-719, doi:10.1109/ted.2004.825805, and D. Ielmini, A. L. Lacaita, D. Mantegazza, IEEE TED 54(2), 2007, pp. 308-315, doi:10.1109/ted.2006.888752. Both DOIs resolve; neither paper was read. Published exponents depend on the material and the fit window (a few hundredths to about 0.12), so the lab’s single 0.1 is a teaching value. The lab’s t0 of one second, and its choice to scale each cell’s exponent by (1 minus its level) so a fully low cell does not drift and a fully high one drifts fully, are the lab’s own.
    • Converters. “ADCs account for 58% of tile power and 31% of tile area” in an accelerator built on 8-bit converters, and nearly half the chip power: A. Shafiee et al., “ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars”, ISCA 2016, doi:10.1109/isca.2016.12. Read: the Table I discussion and the conclusion. A copy of the paper is saved in the library. The lab’s converter is its own: it divides the largest sum the inputs could make (every weight at the highest conductance) into 2^bits minus 1 equal steps and rounds each column to the nearest step. It models no converter power, area or noise.
    • Glossary. Fourteen added terms (compliance, forming, valence-change memory, electrochemical metallization, threshold switching, self-rectifying, nonlinearity, dynamic range, multiply-accumulate, von Neumann, write-verify, multi-level cell, random telegraph noise, drift) are textbook-level definitions and carry no numbers.

    Depth pass (0.5.0)

    This pass added five side trips (6a to 10a) and two sidebars. In this section “read” means the paper was opened and the statement the lab relies on was found in it. “Resolved” means the DOI resolves to the named paper (the Crossref record is saved in the library) and nothing more was done: the paper is behind a paywall or the publisher blocks automated access. A resolved paper describes the idea a panel draws, and none of its numbers is used.

    Read

    • D. Joksas et al., “Nonideality-aware training for accurate and robust low-power memristive neural networks”, Advanced Science 9(17), 2022, doi:10.1002/advs.202105784 (open access). Used for the differential pair (each weight proportional to the difference of two conductances, picked symmetrically around the average conductance) and for the measured 128 by 64 tantalum-oxide crossbar in which 10.1% of the devices counted as stuck (a device whose conductance range was under half the median range). Side trip 10a uses 10.1%; the 1% of pairs with both cells stuck is arithmetic (0.101 squared).
    • D. Joksas et al., “Committee machines: a universal method to deal with non-idealities in memristor-based neural networks”, Nature Communications 11, 4273, 2020, doi:10.1038/s41467-020-18098-0 (open access). Used for the statement that little can be done about fully stuck devices (side trip 10a) and for line resistance accumulating along the bit lines of a crossbar.
    • T. Gokmen and Y. Vlasov, “Acceleration of deep neural network training with resistive cross-point devices: design considerations”, Frontiers in Neuroscience 10, 333, 2016, doi:10.3389/fnins.2016.00333 (open access). Used for the budget of at most 10% voltage drop along a line, defined as N x R_line / R_device (side trip 9a, where R_line is the lab’s total line resistance, N times the wire resistance of one segment, so the cell resistance needed is 10 x N x N x the wire resistance), and for up and down conductance steps having to match to within about 10% to keep the error penalty small (the weight-cell sidebar).
    • P. Sun et al., “Thermal crosstalk in 3-dimensional RRAM crossbar array”, Scientific Reports 5, 13504, 2015, doi:10.1038/srep13504 (open access). Used for the statement that heat from a reset can degrade a neighboring cell and that this worsens as the feature size shrinks (side trip 6a). No number is used.
    • W. W. Koelmans et al., “Projected phase-change memory devices”, Nature Communications 6, 8181, 2015, doi:10.1038/ncomms9181 (open access). Read: a projection segment of non-insulating material sits in parallel with the phase-change material, and at low fields the read current flows through it past the amorphous region, so the resistance read is decoupled from the part that drifts, and the devices showed low drift. Used for the one-sentence description of projected memory in chapter 10 and its glossary term; no number is used.
    • A. Shafiee et al., ISAAC, ISCA 2016, doi:10.1109/isca.2016.12 (already listed). Used for bit slicing: a 16-bit weight spread across eight 2-bit cells in a row, with the pieces added digitally (side trip 9a).
    • S. Pi et al., “Memristor crossbar arrays with 6-nm half-pitch and 2-nm critical dimension”, Nature Nanotechnology 14, 2019, doi:10.1038/s41565-018-0302-0. Read as the arXiv preprint (arXiv:1804.09848, titled “Memristor crossbars with 4.5 terabits-per-inch-square density and 2 nm dimension”). It describes crossbars with 2 nm cells and is the background for the lab’s picture of how small a crossing can be. No number from it is used.

    Resolved, not read

    These were listed or cited as the origin of an idea and the DOI resolves. They were not read, and the page quotes nothing from them.

    • D. Kau et al., IEDM 2009, doi:10.1109/iedm.2009.5424263: a stackable crosspoint phase-change memory with a threshold selector. Side trip 7a draws a window of 1.2V, a teaching value that sits near the one volt of SET-versus-RESET dynamic range the paper’s abstract reports.

    • H.-S. P. Wong et al., “Metal-oxide RRAM”, Proceedings of the IEEE 100(6), 2012, doi:10.1109/jproc.2012.2190369 (unchanged: resolved, not read).

    • S. Ambrogio et al., Nature 558, 2018, doi:10.1038/s41586-018-0180-5 (unchanged: resolved, not read).

    • D. Ielmini and H.-S. P. Wong, “In-memory computing with resistive switching devices”, Nature Electronics 1, 2018, doi:10.1038/s41928-018-0092-2: resolved, not read. Behind a paywall.

    • D. Ielmini and G. Pedretti, “Device and circuit architectures for in-memory computing”, Advanced Intelligent Systems, 2020, doi:10.1002/aisy.202000040: open access, but the publisher’s site blocked an automated fetch, so it was not read.

    • G. W. Burr et al., “Access devices for 3D crosspoint memory”, Journal of Vacuum Science and Technology B 32, 2014, doi:10.1116/1.4889999: resolved, not read.

    • B. Govoreanu et al., “Selectors for high density crosspoint memory arrays: design considerations, device implementations and some challenges ahead”, ICICDT 2015, doi:10.1109/ICICDT.2015.7165872: resolved, not read. Side trip 7a draws the V/2 scheme it describes.

    • E. Linn et al., “Complementary resistive switches for passive nanocrossbar memories”, Nature Materials 9, 2010, doi:10.1038/nmat2748: resolved, not read. Chapter 7 describes the complementary resistive switch it introduced.

    • A. Chen, “Nonlinearity and asymmetry for device selection in cross-bar memory arrays”, IEEE Transactions on Electron Devices 62, 2015, doi:10.1109/ted.2015.2450712, and J.-J. Huang et al., “One selector-one resistor (1S1R) crossbar array for high-density flexible memory applications”, IEDM 2011, doi:10.1109/iedm.2011.6131653: resolved, not read. Side trip 7b works out the same analysis (a diode needs a nonlinearity above (n-1) squared, a nonlinear selector above (n-1) over 2); the lab’s tests check the closed forms against the misread criterion they come from.

    • A. Flocke and T. G. Noll, “Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory”, ESSCIRC 2007, doi:10.1109/esscirc.2007.4430310, and C.-L. Lo et al., “Dependence of read margin on pull-up schemes in high-density one selector-one resistor crossbar array”, IEEE Transactions on Electron Devices 60, 2013, doi:10.1109/ted.2012.2225147: resolved, not read. Side trip 7b says a bare array with floating idle lines cannot be read past 3 by 3, which the lab’s tests confirm from the same misread criterion. Since 0.5.1 the circuit solve’s read margin uses the same two worst-case backgrounds (a high read with every other cell low, a low read with every other cell high), so the main stage agrees with 7b: it reads at 3 by 3 and misreads from 4 by 4. R. Ciprut and E. G. Friedman, IEEE Transactions on Very Large Scale Integration Systems 25(1), 2017, doi:10.1109/TVLSI.2016.2570120 (read): defines the read margin as the difference between the low and high sense currents and takes the worst case for each state separately, which is the principle used here; its models use selectors and a different pattern of idle cells, and none of its numbers is used.

    • I. G. Baek et al., “Realization of vertical resistive memory (VRRAM) using cost effective 3D process”, IEDM 2011, doi:10.1109/iedm.2011.6131654: resolved, not read. Chapter 8 says a vertical design needs about one critical mask whatever the number of layers; that is stated without a number.

    • I. Giannopoulos et al., “8-bit precision in-memory multiplication with projected phase-change memory”, IEDM 2018, doi:10.1109/IEDM.2018.8614558: resolved, not read. Chapter 10 says a published demonstration reached 8-bit multiplication with projected phase-change memory, which is the claim of its title.

    • K. Moon et al., “RRAM-based synapse devices for neuromorphic systems”, Faraday Discussions 213, 2019, doi:10.1039/c8fd00127h: resolved, not read (the publisher’s site blocks automated access). The weight-cell sidebar lists targets from reviews of this kind, as teaching values.

    • Z. Wang et al., “In situ training of feed-forward and recurrent convolutional memristor networks”, Nature Machine Intelligence 1, 2019, doi:10.1038/s42256-019-0089-1: resolved, not read. The sidebar on noisy writes says some designs accept one blind update at a time instead of verifying each write.

    • H. Abbas et al., Nanoscale, 2020, doi:10.1039/d0nr02335c: resolved, not read. Chapter 7 says some oxide cells act as a volatile threshold switch at a low compliance current and as non-volatile memory at a higher one.

    • Z. Sun, G. Pedretti, E. Ambrosi, A. Bricalli, W. Wang and D. Ielmini, “Solving matrix equations in one step with cross-point resistive arrays”, Proceedings of the National Academy of Sciences 116(10), 2019, doi:10.1073/pnas.1815682116: read in full (open access). Chapter 11 and side trip 11a rest on it: the feedback circuit and the virtual ground, A x = b solved by settling, the input currents of 20, 100 and 100 microamps and the 3% agreement, the stability rule (every diagonal element of the inverse positive), the N runs for a matrix inverse, the settling-time limit of a few nanoseconds, and the simulated 10% conductance spread and wire-resistance errors.

    • Z. Sun, G. Pedretti, A. Bricalli and D. Ielmini, “One-step regression and classification with cross-point resistive memory arrays”, Science Advances 6(5), 2020, doi:10.1126/sciadv.aay2378: read in full (open access). The sidebar on fitting a line rests on it: the pseudoinverse circuit, the 4.86% and 0.82% errors on the two weights, and the settling time near a microsecond.

    • C. Li et al., “Analog content-addressable memories with memristors”, Nature Communications 11, 2020, doi:10.1038/s41467-020-15254-4: read in full (open access) for its description of the cell, a lower and an upper bound stored in two memristors. The sidebar says only that, with no number.

    What each new panel rests on

    • 6a, writing a cell. The counts of stressed cells (2(n-1) at half the write voltage under V/2, every other cell at a third under V/3) are arithmetic about the schemes, and the voltages come from the lab’s own circuit solve. The 2V write and the 2Ω wire are teaching values. The diode-in-each-cell step counts cells by the bias they see: one forward-biased, 2(n-1) with a small bias, (n-1) squared reverse-biased. The line voltages (5V, 0.8V, 0V and 4.5V for a program) are example values in the style used for phase-change arrays with diode selectors and are teaching values.

    • 7a, selector threshold. The condition that the median set threshold exceed the window plus 4 sigma of the reset spread plus 8 sigma of the set spread follows from requiring half the write voltage to stay below the lowest set threshold, with each spread taken at four sigma. The tests check the closed form against the inequality it comes from. The 1.2V window, the three thresholds and the spreads are teaching values.

    • 7b, selector nonlinearity. The two closed forms are checked in the tests against the misread criterion (two parallel resistances compared) for every side and on/off ratio. The alpha values are teaching values.

    • 9a, signed weights. The pair and the shared reference column are solved on the same circuit as chapter 9. Bit slicing is arithmetic (ten levels per cell). The 16-bit weight across eight 2-bit cells is from ISAAC. The drop budget formula is from Gokmen and Vlasov.

    • 10a, working around damage. Intensity-aware mapping is the lab’s own demonstration on its own solve: the rows are reordered busiest input first, the weights move with them, and the ideal sums are unchanged. The partner repair is the lab’s own model, with a stuck cell taken to sit at the lowest conductance (a teaching choice) and the 10.1% share from Joksas et al.

    • Sidebars. The weight-cell targets are teaching values taken from published reviews of synapse devices, which do not agree on every number. The 10% balance of up and down steps is from Gokmen and Vlasov. The arithmetic of about three million updates in a 60,000-image, 50-epoch run is 60,000 times 50.

    • 11, solving Ax = b. The circuit and its stability rule are from the first paper above. The matrices, the input currents of the two other steps and the 8 by 8 system are teaching values; the lab solves the whole network (cells, wires, an amplifier of finite gain on every row) by dense elimination and the tests check it against the exact solution, against the diagonal perturbation (A + diag(row sums) / gain) V = b that a finite gain gives, and against the multiplier solve turned on its side.

    • 11a, limits. The error figures on the stage are the lab’s own, from teaching values. The paper says only that the amplifier’s high gain establishes the virtual ground, so the gain numbers are the lab’s, and so is the observation that the errors can partly cancel. The one-norm condition number is the lab’s choice of norm.

    Not used

    • The thermal and write-margin papers’ numbers: none is used.

    How the page maps to this file (0.9.0)

    The page is now six sections: read (formerly chapters 3 to 5), hold the idle lines and write (6 and 6a), block the idle cells (7), rows in and columns out (9, 10), signs and repairs (9a, 10a) and solve (11, 11a). In the sections above, “chapter” and “side trip” name those earlier walkthrough parts, and each claim is still on the page: the drawings of chapters 1 and 2 (the switching loop and the programming curve), 7a, 7b and 8 became sentences in How it works, and the two sidebars became shorter ones in the same place. Their model code and tests are unchanged, so the closed forms and anchor values named above are still checked.

    Detail moved off the page

    These numbers and statements were in the page’s prose before 0.9.0 and are kept here in full. Each carries the same status as above.

    • Programming curve. A moderate pulse of current crystallizes a phase-change cell, which sets it. A much bigger pulse melts part of it and a quick falling edge freezes the melt glassy, which resets it. A set cell stays set until the current is big enough to melt it, and once the pulse melts the cell it no longer matters which state the cell started in. The anchor currents and pulse lengths are the ones in the Programming curve section above.
    • Cell types. A resistive cell sets by a filament forming across the layer: by moving oxygen vacancies in a valence-change cell, by growing a metal bridge in an electrochemical metallization cell. A fresh cell often needs a one-time forming pulse and a cap on the current while it sets, its compliance current, helps decide how low its resistance ends up.
    • Selector reasoning. The selector threshold sits between half the read voltage and the whole read voltage. The selector shields every idle cell. The transistor cuts off the other rows but leaves the selected row’s other cells at half voltage, and needs room beside each cell, which a stacked selector does not. On a 2,000 by 2,000 tile there are four million idle cells, so if their combined leak must stay below one 100 microamp program current, each must leak under 25 pA, which is why a selector’s off current matters more than its on current. A self-rectifying cell usually pays with poorer endurance and a less linear, less symmetric response. A complementary resistive switch presents high resistance to a read in both states, so the array’s resistance does not depend on what is stored, at the price of a read that destroys the value. Some oxide cells act as a volatile threshold switch at a low compliance current and as a non-volatile memory at a higher one.
    • Threshold window. For a cell that pairs a phase-change element with an ovonic threshold switch, a cell in the set state turns on at a lower voltage than one in the reset state. Half the write voltage must stay below the lowest set threshold and the write voltage must turn on the highest reset threshold, so the median set threshold must exceed the window plus four standard deviations of the reset spread plus eight of the set spread. The 1.2V window, the three thresholds (1.0V, 1.6V, 2.4V), the 0.03V opening spread and the four-sigma tail are teaching values.
    • Selector nonlinearity. A diode needs alpha above (n-1) squared and a nonlinear selector above (n-1) over 2. At 16 by 16 these are 225 and 7.5, and at 1,024 by 1,024 about a million and 512. With no selector and floating idle lines the same test fails past 3 by 3, however large the on/off ratio.
    • Write with a diode in each cell. About n squared diodes block at once, 2n carry a small bias and one is forward-biased. Heat from a reset can push a neighbor back from low resistance toward high, more seriously as cells shrink (Sun et al., above).
    • Decks. A bare crossing is 4F squared, lines every 2F in both directions. Each doubling of decks halves the area per bit. Each deck brings its own cell and selector layers and its own patterning, so cost per bit falls less. A vertical design needs about one critical mask whatever the number of layers, where stacked crosspoint repeats its patterning for every deck.
    • Weights. Dynamic range of 100 here. Converters: 58% of tile power and 31% of tile area in one design with 8-bit converters (Shafiee et al., above). Each cell holds ten levels and bit slicing multiplies the levels by ten per cell. To keep the drop along a line inside a tenth of the input a cell must be at least about ten times the side of the array times the line’s total resistance. The weight-cell targets in published reviews: about a hundredfold between lowest and highest conductance, at least 32 distinguishable levels, switching energy under 10 fJ, retention of ten years or more and a size down to 10 nm; another review asks for under 1 square micrometer, under 1 microsecond to write or read, under 1 pJ per switch, about a billion write cycles, noise under 0.5% of the weight range and about six bits per device. They do not agree on every number. Up and down steps must match within about 10%. Inference wants states that last hours to days or longer, training can live with a few hundred seconds. A 60,000-image, 50-epoch run is at most about three million updates, yet a review asks for ten thousand cycles because only some cells are updated per pass. Most devices land between 2 and 100 in dynamic range.
    • Write noise. Programming is random in itself because ions move at random in the film. Write-verify reads back and nudges until close, which costs time and energy, more as levels get closer. Some designs accept one blind update at a time. Stepped pulses make the update more linear, the same idea as the staircase a NAND flash uses.
    • Solver detail. The settling time is the amplifier’s, a few nanoseconds in advanced CMOS, where a digital solver does a number of operations that grows as the cube of the size. Inverting a matrix takes one run per column. The first system uses the input currents of a published 3 by 3 experiment, 20, 100 and 100 microamps, whose outputs matched the analytical solution to within 3%. At a gain of 100 the error is about 1%, and each tenfold of gain takes about a tenth of it away. A published simulation of a 100 by 100 system found an error near 10% with a 10% spread in conductance and between about 10% and 30% with the wire resistance of two process nodes, and concluded that the error is set mostly by how the cell resistance compares with the wire resistance. The numbers the stage shows are the lab’s own.
    • Fitting and search. A straight-line fit chooses weights w to minimize the error of X w against y, with the answer (X transpose X) inverse X transpose y. A six-point experiment came within 4.9% on the intercept and 0.8% on the slope, and a simulation put the settling time near a microsecond. An analog content-addressable memory stores a range in each cell, one memristor for the lower bound and one for the upper.