Sources

NAND Cell Lab is a teaching model. Its constants are teaching values chosen to show the shape of the physics, not measurements of any part, and nothing in the lab is vendor data. Earlier versions drew several of the mechanisms below as their own panels (neighbor coupling, program inhibit, sensing, source-line bounce, cross-temperature reads, valley search, ECC strength, prone cells, hole taper, 3D density and 1/f noise). The page now draws one cell and one chart; the models and their tests stay in src/lib/nand-cell-*.ts, and these sections still say where their numbers come from. This file lists the papers that describe the mechanisms the lab draws, and says plainly which numbers are the lab’s own.

Neighbor coupling (0.3.0)

The mechanism: a cell’s floating gate or charge-trap layer shares field with its neighbors, so programming a neighbor after the victim moves the victim’s threshold voltage with no pulse aimed at it.

Lee, Hur and Choi, “Effects of floating-gate interference on NAND flash memory cell operation”, IEEE Electron Device Letters 23(5), 264 to 266, 2002. doi:10.1109/55.998871. Describes capacitive coupling between floating gates producing inaccurate sensing of threshold voltage. The lab uses the idea (a victim shift summed over neighbors, each weighted by a coupling ratio), not the paper’s numbers.
Goda and Parat, “3-D NAND Technology Achievements and Future Scaling Perspectives”, IEEE Trans. Electron Devices 67(4), 2020. doi:10.1109/ted.2020.2968079. Says 3D gate-all-around NAND has a larger cell and better shielding between cells, which reduces cell-to-cell interference compared with planar NAND. This is why the lab credits the wrap-around control gate and the larger cell, not the insulating nitride, for the drop. The lab takes the size of the drop (roughly five-fold) as a teaching value, not a number from the paper.
Goda and Parat, “Scaling directions for 2D and 3D NAND cells”, IEDM 2012. doi:10.1109/iedm.2012.6478961. Abstract only: describes NAND cell scaling directions for 20nm and beyond, a planar floating-gate cell, and the key requirements for 3D NAND. Not used for any number.

Measured presets (0.14.0): the “Measured 2y-nm planar” and “Measured 1x-nm planar” presets use the coupling coefficients in Table 2 of Cai, Ghose, Haratsch, Luo and Mutlu, “Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives”, Proc. IEEE 105(9), 2017 (arXiv 1706.08642), which that paper takes from Cai et al.’s earlier program-interference characterization (ICCD 2013). Word-line neighbor 0.060 and 0.110, bit-line neighbor 0.032 and 0.055, diagonal neighbor 0.012 and 0.020, for 2y-nm and 1x-nm. The same section says 1x-nm MLC cells store only about 100 electrons, which the 1x-nm preset uses for its electron count. The 2y-nm preset keeps the planar teaching count of 400, because no figure is published for that node. The earlier ICCD paper itself was not opened.

The lab’s own numbers (teaching values, in src/lib/nand-cell-coupling.ts; the planar floating gate and 3D charge-trap columns, not the measured presets):

Value	Planar floating gate	3D charge trap
Coupling ratio, next word lines	0.08	0.016
Coupling ratio, next bit lines	0.03	0.006
Coupling ratio, diagonals	0.01	0.002
Electrons across the 6 V window	400	1500

The fine-pass share of a neighbor’s move in two-pass programming is 0.2. Each of these is chosen to contrast the two builds, not taken from a paper. The only claims the preset values are meant to carry: planar floating gates couple more than 3D charge-trap cells, denser cells leave fewer electrons between levels, and two-pass programming absorbs most of the shift.

3D charge-trap behaviour (0.4.0)

The mechanism: in 3D charge-trap NAND the early part of retention loss is steep, the threshold shift grows with the logarithm of time, and the erased state rises. Under P/E cycling the erased state shifts and widens far more than the programmed states. The lab’s simplifications, not findings of these papers: retention does not widen the states, and wear and read disturb are linear.

Luo, Ghose, Cai, Haratsch and Mutlu, “Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation”, Proc. ACM Meas. Anal. Comput. Syst. 2(3), 2018. doi:10.1145/3224432. Measured these trends on 30 to 40 layer MLC parts from one vendor.
Luo, Ghose, Cai, Haratsch and Mutlu, “HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness”, HPCA 2018. doi:10.1109/hpca.2018.00050. Reports about 1.04 eV for retention loss in 3D charge-trap parts, against the 1.1 eV used for planar parts.

The lab’s own numbers (teaching values): 0.06 V per decade of time for the top state, 0.04 V per decade of erased-state rise, 0.4 V erased-state shift after a million reads, linear wear, and 1.04 eV. The papers measured older two-bit parts; the lab claims the shape, not their numbers. The tests check that the mode is off by default, that it lifts the erased state, that it never widens a state, that loss grows with level and about one step per decade, and that read disturb doubles when reads double.

Program inhibit (0.5.0)

The mechanism: the cells on the programmed wordline in the other strings are inhibited by leaving their channels floating and raising every wordline in the string, so the channel boosts with the wordlines and the field across the cell falls.

Suh et al., “A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme”, IEEE JSSC 30(11), 1149 to 1156, 1995. doi:10.1109/4.475701. Introduced self-boosted program inhibit and incremental step pulse programming.

The lab’s own numbers (teaching values, in src/lib/nand-cell-inhibit.ts): a boost ratio of 0.75 for a planar string and 0.95 for a 3D gate-all-around string, a 32 wordline string by default, and 20 V program and 9 V pass voltages. Boosted channel = ratio x ((N - 1) x Vpass + Vpgm) / N. Program disturb stress is Vpgm minus that channel; pass disturb stress is Vpass on an unselected wordline of the grounded string. These are the field voltages, not failure rates, and the lab does not say where either becomes a failure. The tests check the formula, that the stresses cross at the balance point, and that the gate-all-around string balances at a lower pass voltage.

Sensing (0.6.0)

The mechanism: the cell current of a series string charges or discharges a capacitor, and the read waits for it to move by a swing. Shielded-bitline sensing does it on the whole bitline and reads half the bitlines at a time; all-bitline sensing does it on a small sense node.

Tanaka et al., “A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory”, IEEE JSSC 29(11), 1366 to 1373, 1994. doi:10.1109/4.328638. Shielded-bitline sensing.
Cernea et al., “A 34 MB/s MLC write throughput 16 Gb NAND with all bit line architecture on 56 nm technology”, IEEE JSSC 44(1), 2009. doi:10.1109/jssc.2008.2007152. All-bitline sensing.

The lab’s own numbers (teaching values, in src/lib/nand-cell-sense.ts): a 2 pF bitline, a 30 fF sense node, a 0.5 V bitline, a 100 kOhm on-resistance per cell, and a 0.4 V sensing swing. String current = 0.5 V / ((N - 1) x 100 kOhm); evaluation time = swing x capacitance / current. This is only the evaluation: a real read also precharges, settles and latches, so the page read time is longer. The tests check the formula, that the all-bitline time is shorter by the capacitance ratio, and that longer strings are slower.

What a code buys (0.7.0)

The mechanism: a code that corrects up to t bit errors in an n-bit codeword fails when more than t bits are wrong. With independent errors that is a binomial tail. A BCH code over GF(2^m) needs about m x t parity bits.

JEDEC JESD218 (SSD requirements and endurance test method) sets the client uncorrectable bit error ratio at 10^-15 and the enterprise one at 10^-16, as presented in the JEDEC overview deck at jedec.org by Alvin Cox. The lab uses 10^-15.

The lab’s own arithmetic (in src/lib/nand-cell-ecc.ts): codeword = data + m x t parity bits with the smallest m that fits; failure = the binomial tail summed in log space; UBER is approximated as the failure probability times the bits wrong in a failed codeword (at least t + 1, or n x p when nearly every codeword fails) over n. Errors are taken as independent and equal for every bit, and the lab models BCH only; real controllers use LDPC with soft decoding, which tolerates a higher raw error rate. The tests check the tail against a direct sum, the 14-bit field for a kilobyte, that about 40 bits per kilobyte are needed at a raw error rate of 10^-3, and that a stronger code never does worse.

Electron-counting floor (0.7.1)

The mechanism: programming moves charge as whole electrons that arrive at random, so for small charge packets a step that delivers N electrons has a spread of about the square root of N (it becomes sub-Poissonian for large packets), and in volts that is the square root of (step x volts per electron).

Monzio Compagnoni et al., “Ultimate accuracy for the NAND flash program algorithm due to the electron injection statistics”, IEEE Trans. Electron Devices 55(10), 2008. doi:10.1109/ted.2008.2003230. Measured and modelled this limit.

The lab’s own numbers: the volts per electron come from the same teaching electron counts as the coupling panel (400 planar, 1,500 3D across the lab’s window). The floor is a lower bound on spread and the lab does not add it to the state widths on the chart.

A hole that narrows (0.8.0, real values in 0.11.0)

The mechanism: a 3D cell’s films wrap a cylindrical channel, and in a cylinder the field falls as 1/r, so the tunnel oxide at the channel sees more field than the same films laid flat, and more again where the hole is narrower. The etched hole narrows toward the bottom of the stack, so the lower wordlines program and erase faster at the same voltage, and the chip trims the program pulse by wordline.

Park et al., “Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming”, ISSCC 2014. doi:10.1109/ISSCC.2014.6757458. Samsung’s first V-NAND. The lab’s 120nm starting hole and 160nm starting pitch are teaching values, not figures from the paper. Flash Foundations Part 4 quotes TechInsights’ teardown of the next generation with the same 120nm hole.
Nowak et al., “In-depth analysis of 3D silicon nanowire SONOS memory characteristics by TCAD simulations”, IMW 2010. doi:10.1109/imw.2010.5488387. A TCAD study of 3D nanowire SONOS cells. Its abstract gives no film thicknesses, so the lab’s 5/6/8nm stack is a teaching value.
Ishiduki et al., “Optimal device structure for Pipe-shaped BiCS Flash memory”, IEDM 2009. doi:10.1109/iedm.2009.5424261. A 90nm hole could not erase below 0V where a 66nm hole reached below -3V, the effect this panel draws. The slider spans are the lab’s own choices (illustrative).
Kang et al., “256 Gb 3 b/Cell V-NAND Flash Memory With 48 Stacked WL Layers”, IEEE JSSC 52(1), 2017. doi:10.1109/JSSC.2016.2604297. The abstract describes wordline variations in the vertical stack and a variable-pulse scheme to cope with nonuniform wordline characteristics.
Amoroso et al., “Semi-Analytical Model for the Transient Operation of Gate-All-Around Charge-Trap Memories”, IEEE TED 58(9), 2011. doi:10.1109/ted.2011.2159010.
Lenzlinger and Snow, “Fowler-Nordheim Tunneling into Thermally Grown SiO2”, J. Appl. Phys. 40, 1969. doi:10.1063/1.1657043. Standard thermal-oxide values (barrier 3.1 to 3.2 eV, effective mass ratio 0.42 to 0.5; the 1969 paper is not saved), here 3.2eV and 0.42, behind B = 6.83e7 x sqrt(0.42) x 3.2^1.5 V/cm = 253MV/cm.

The lab’s own arithmetic (in src/lib/nand-cell-taper.ts): three films in series as coaxial cylinders, with no stored charge, so the field at radius r is V / (eps r sum(ln(r_out / r_in) / eps)). Oxide eps 3.9, nitride 7.5. A wide hole gives back the flat-film field, which the tests check, and the tunnel to blocking field ratio matches a published field-enhancement curve to within 7% from 5 to 100nm of channel radius. The 90nm default bottom and the straight taper between the ends are the lab’s choice inside the published range. The start trim is the voltage at which a narrower wordline reaches the top wordline’s tunnel field; real chips trim by measurement, and stored charge, the channel’s own voltage and the wordline’s resistance all move the numbers. The model has no breakdown limit and flags fields above 18MV/cm.

Where 3D density comes from (0.9.0)

The mechanism: seen from above, the array is a grid of pillars, and each pillar stores bits per cell on every layer, so the array holds layers x bits per pillar footprint. Staggering alternate rows shrinks the row pitch by cos 30 degrees when the two pitches match, and each slit adds its width shared over the rows between slits. The die adds periphery and the staircase that contacts each layer.

Kang et al., “256 Gb 3 b/Cell V-NAND Flash Memory With 48 Stacked WL Layers”, IEEE JSSC 52(1), 2017. doi:10.1109/JSSC.2016.2604297. The 256Gb 48-layer TLC die; its abstract gives 2.6Gb/mm².
Kim et al., “A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory”, IEEE JSSC 53(1), 2018. doi:10.1109/JSSC.2017.2731813. Table I compares the earlier dies: 1.86Gb/mm² for the 128Gb 32-layer TLC die and 2.62Gb/mm² for the 256Gb 48-layer die. Both anchors are the values Eyes on Flash’s NAND die dataset records from that table.
Tanaka et al., “A 768Gb 3b/cell 3D-floating-gate NAND flash memory”, ISSCC 2016. doi:10.1109/ISSCC.2016.7417947. 768Gb in 179.2mm², 4.29Gb/mm², with CMOS under the array.
Shibata et al., “A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology”, IEEE JSSC 55(1), 2020. doi:10.1109/JSSC.2019.2941758. 8.5Gb/mm².
The lab’s 160nm hole pitch is a teaching value (Park et al., ISSCC 2014, above, is cited for 128Gb and 24 layers only). Published array efficiencies: 60 to 81% for 2D and conventional 3D dies with the periphery beside the array (no primary source is saved for that range); up to about 85% with the core circuits under the array (Tanaka et al., ISSCC 2016); about 95% with periphery and core both under it (Aritome, IMW 2016, via a secondary survey; the paper itself is not saved). TechInsights reports about 85% for Intel/Micron CuA dies against 60 to 70% without CuA, and measured 84.9% (32L), 92.0% (64L) and 91.5% (96L) for Intel/Micron CuA dies (Choe, FMS 2019).

The lab’s own arithmetic (in src/lib/nand-cell-density.ts): area per pillar = pitch x (row pitch + slit width / rows between slits); array density = layers x bits x 10^12 / area / 2^30, in the binary gigabits die capacities are quoted in; die density = array density x the array share. The 160nm pitch is Samsung’s first V-NAND pitch and the 70% default array share sits inside the published 60 to 81%. Teaching values: the 120nm slit width and 4 rows between slits. Real arrays also lose area to dummy and select layers, which the lab leaves out. The “to match” readout is the array share that would turn this array into the 48-layer TLC die’s density, whatever bits per cell you pick; it is only as good as the pitch you set, since the lab does not know that die’s pitch.

Many traps and 1/f noise (0.3.0)

The mechanism: a single oxide trap makes random telegraph noise with one corner frequency. Many traps with log-uniformly spread time constants sum to a spectrum that falls as 1/f.

M. J. Uren, D. J. Day and M. J. Kirton, “1/f and random telegraph noise in silicon metal-oxide-semiconductor field-effect transistors”, Applied Physics Letters 47, 1195, 1985. doi:10.1063/1.96325. Telegraph noise in small MOSFETs.

The lab’s own numbers: trap time constants spread over three decades above 2 samples, each trap’s swing is the lab’s existing RTN swing (0.3 V), and the spectrum is computed from a simulated trace by FFT. The tests check that one trap’s corner lands at 1 over 2 pi tau within 10 percent and that 30 traps over four decades give a slope of minus one within 0.2.

Retention and read disturb shapes (0.10.0)

The mechanism: during retention the high states lose charge through trap-assisted tunneling while the low states, which hold holes, rise as those leak away, and every state widens. Read disturb lifts the low states most, because the pass voltage stresses a low-voltage cell hardest, and it grows as a power of the read count. The top state’s left tail dips slightly.

Cai, Ghose, Haratsch, Luo and Mutlu, “Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives”, Proc. IEEE 105(9), 2017; arXiv 1706.08642. Sections 4.4 and 4.5, and Appendix Tables 4 to 6 (TLC, normalized threshold units, about 64 units per state gap). Table 6: the erased state rises 8, 27, 51 and 64 units after 1,000, 10,000, 50,000 and 100,000 reads, which a 0.45 power fits and a logarithm does not; P7 falls 5 units. Table 5: from one day to one year the erased state rises 23 units, P7 falls 7, and every programmed state widens about 30%.

The lab’s own numbers: one TLC state gap of erased-state rise at 100,000 reads (0.67V in this lab’s window), the same volts for every cell type, a (1 - level)^6 weight upward and an 8% dip at the top; 0.05V per decade of erased-state rise, falling off as (1 - level)^2; retention widening on every programmed state alike. Table 4 shows wear widening that speeds up with cycles rather than slowing as a square root, so the lab keeps its 0.8 power. Past 100,000 reads the power law is extrapolated, and by a million reads the low states of a TLC or QLC cell have run into each other, which is why drives refresh a block long before that. 3D mode keeps its own shapes.

Program order and source-line bounce (0.12.0)

The mechanism, program order: word lines are programmed in sequence, so a victim’s word-line-below neighbors are finished before it. All-bitline programming writes every cell on a word line together, so the same-word-line neighbors are finished at the same time and only the row above (the next word line and its two diagonals) disturbs the victim afterward. Shielded-bitline (even/odd) programming writes the even bitlines first and the odd ones second, so an even victim still has its two bit-line neighbors to come.

Cai, Ghose, Haratsch, Luo and Mutlu, “Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives”, Proc. IEEE 105(9), 2017; arXiv 1706.08642, section 4.3: in modern all-bitline NAND the cells on a word line program together and word lines program in sequence, so the neighbors on the word line below and on the same word line induce no interference after the victim is fully programmed.
Lee, Hur and Choi (2002), above: capacitive interference between floating gates. The even/odd consequence, that programming the odd cells later shifts already-programmed even cells, is the one that paper and its successors describe.

The lab’s own arithmetic (in src/lib/nand-cell-coupling.ts): an eight-entry mask of which neighbors program after the victim, applied to the existing coupling sum. The coupling ratios are unchanged teaching values. The worst-case option keeps all eight neighbors last, which no real order does.

The mechanism, source line: every conducting string returns its current through one shared source line, whose resistance lifts its voltage; the cell being read then sees a lifted source and reads higher than it is. Erased cells conduct and programmed ones do not, so the rise depends on the data pattern.

Sekar et al., “Non-volatile storage with compensation for source voltage drop”, US patent 7,606,072 (SanDisk). States that parallel sensing sends a substantial current through the source line, that its finite resistance gives an appreciable drop, and that the drop can be as high as 0.3 V in some NAND flash chips. The 0.3 V marker on the figure is that figure.
A source-line resistance of 10 to 20 ohms carrying about 10 mA gives about 100 to 200 mV, and the lab assumes the read shift is 2 to 3 times that rise (once the falling drain voltage and the body effect are counted). These are the values the lab uses as its defaults and band. They come from a published treatment of NAND sensing that points to the patent above for the factor; the patent text itself does not state the factor or the resistance, so those are left uncited here. These come from a published treatment of NAND sensing (ch. 9) which gives K = 2 to 3 from experimental results it attributes to a patent; the saved patent text itself does not state K or the resistance.

The lab’s own numbers (in src/lib/nand-cell-sourceline.ts): shielded sensing reads half the bitlines at once, so it draws half the current of all-bitline sensing (the bitline share in nand-cell-sense.ts); the 5 to 30 ohm slider range; the share of strings conducting; and ideal compensation, which cancels the read shift entirely (real circuits leave some residual, which the lab does not size). The cell margins are this lab’s teaching windows, so which cell type fails first is the lab’s, not a measurement.

How big is the step (0.13.0)

The mechanism: the threshold step one trap causes follows an exponential distribution, e to the minus step over lambda, because current finds a path through the channel around the trap and the effect of one trapped electron varies from cell to cell. Lambda, in millivolts per decade, is the number that characterizes RTN in an array. Reading more cells reaches further down the tail.

Spinelli, Malavena, Lacaita and Monzio Compagnoni, “Random Telegraph Noise in 3D NAND Flash Memories”, Micromachines 12(6), 703, 2021. doi:10.3390/mi12060703. States the exponential law and slope for planar and 3D arrays; that a 3D array shows one exponential over most cells while planar arrays show exponential tails departing from a central distribution; that the 3D slope is lower than planar; that planar RTN does not depend on temperature while 3D slope falls at higher temperature; and, quoting Tega et al. (IEDM 2006), threshold shifts reaching 700 mV in 90 nm devices. The lab draws the single exponential and does not model the planar core or the temperature dependence.
Monzio Compagnoni et al., “Cycling effect on the random telegraph noise instabilities of NOR and NAND Flash arrays”, IEEE Electron Device Letters, 2008. The tail rises with cycling as a power law of exponent 0.29 while its slope is nearly independent of cycling. Not opened in this pass; the number is as reported in a survey of reliability work, so treat it as a pointer to that paper.

The lab’s own numbers (in src/lib/nand-cell-rtn-step.ts): the slope slider’s 20 to 200 mV per decade range and its 115 default, picked so that a million cells reach about 700 mV, the value measured; the cell counts; and the largest step as slope times the log of the cell count, which is where the tail falls to one cell. The cell margins are the lab’s teaching windows. The panel does not change the fixed 0.3 V swing used by the single-cell trace and the RTN mode.

Programmed hot, read cold (0.15.0)

Zambelli, Crippa, Micheloni and Olivo, “Cross-Temperature Effects of Program and Read Operations in 2D and 3D NAND Flash Memories”, 2018. Reading at a temperature different from the program temperature produces many fail bits even with compensation; the worst case is program at 70 C, read at 40 C, in mid-1x planar and in 3D TLC; 3D shows up to 15.1 times the same-temperature fail bits where planar shows 1.9 times. That ratio is of fail bits, not volts.
Tanzawa, Tanaka and Takeuchi, US 5,864,504 (Toshiba). The read and verify voltage should follow the cell’s threshold temperature dependence; the worked example uses -2 mV per degree. The lab’s planar 1.5 mV per degree is the typical value given in a published treatment (ch. 11), which also gives about 200 mV over -40 to 90 C and under 20 mV with on-die compensation, the on-die tracking result the panel’s compensation switch reproduces.
The lab’s own choices: the 3 mV per degree for a poly-silicon channel (a teaching value; no published millivolts per degree was found), the symmetric model, and calibrating the references at the program temperature so the figure isolates the cross-temperature penalty.

How the controller finds the valley (0.16.0)

Cai, Ghose, Haratsch, Luo and Mutlu, “Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery”, Proc. IEEE 105(9), 2017 (arXiv 1706.08642), section 5.3 and Figure 24. Disparity-based read reference approximation by binary search: scrambled data puts equal shares of cells in each state, so the controller searches for the reference with 50 percent of cells reading as 0 (MLC middle reference), then 25 and 75 percent for the outer two; extended to TLC the same way. Sampling-based adaptive Vopt discovery improved endurance by 64 percent and cut error-correction latency by 10 percent; a model-based estimate was within 2 percent of the improvement from an ideal Vopt; tuning Vpass per block improved endurance by 21 percent.
Thiers et al., Electronics 2021: the number of errors in ECC-protected metadata read at a calibration voltage picks a threshold-voltage offset from a look-up table, needing up to two metadata reads. The lab uses the method’s outline only. The 510 metadata bits, 21 correctable errors and three table entries are the lab’s teaching values, and the lab builds its own table.
The lab’s own choices: the 0.02 V search resolution (nine reads over the 10 V window), the six ageing conditions behind the table, the 0.04 V step of the blind search, and picking a table entry by the nearest expected metadata error count.

Electrons per 100 mV (0.17.0)

Tanaka et al., ISSCC 2016 paper 7.7, Fig. 7.7.2: electrons per 100 mV of threshold voltage by node, read off a log axis and good to about 10 percent (90 nm about 42, 70 nm 27, 50 nm 16, 34 nm 11, 25 nm 6, 20 nm 3.3, 16 nm 2.7, 3D floating gate about 21). Goda, IEEE Trans. Electron Devices 67(4), 2020, Fig. 5: about 30 electrons per 1 V for sub-20 nm planar and about 250 per 1 V for 3D, which is the source of the lab’s 3D value of 25. The lab table rounds the Tanaka readings.
The relation: delta V = q n / C, with C the capacitance between the control gate and the charge. Compagnoni et al., IEEE TED 55(10), 2008, and IEEE EDL 36(2), 2015 (first detection of single-electron charging), are the measurements behind the single-electron picture.
Lab choices: the lab’s window is 6 V, so 210 electrons across it is 3.5 per 100 mV and 1,500 is 25.

Heavy tails (0.18.0)

The shape: the lab models the programmed-state tails of worn cells as one-sided exponential tails on a Gaussian core (an exponentially modified Gaussian). This shape is the lab’s modeling choice, not a measured result, and every length is a teaching value.
Cai, Haratsch, Mutlu and Mai, “Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis, and Modeling”, DATE 2013 (opened): programmed states are well approximated by a Gaussian (a Beta distribution fits better on average) that shifts right and widens with cycling; the erased state could not be measured on the test chips, which is why the lab gives the erased state no tail. That paper does not itself describe left-sided exponential tails.
The Student’s-t option was added in 0.20.0 (see below).
Lab values: the 50 per volt fresh rate and the factor of 4 growth with wear.

Activation energy (0.19.0)

Luo, Ghose, Cai, Haratsch and Mutlu, “HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness”, HPCA 2018: a least-squares fit to characterization data of 3D charge-trap chips gives Ea = 1.04 eV with a 95 percent confidence interval of 1.01 to 1.08 eV, and Arrhenius’ law holds with a coefficient of determination of about 0.76 (opened; the value is said to be similar across vendors’ charge-trap cells).
The JEDEC convention of 1.1 eV for the accelerated retention mechanism, from the JEDEC SSD specification overview deck (the standard behind the JESD218 retention test). The standard itself was not opened.
The equivalence quoted in the selector note is computed, not quoted: exp(Ea/kB (1/298.15 - 1/343.15)) times 24 hours, about 9.0 months at 1.1 eV and 6.6 months at 1.04 eV.

Student’s t tails (0.20.0)

Luo, Ghose, Cai, Haratsch and Mutlu, “Enabling Accurate and Practical Online Flash Channel Modeling for Modern MLC NAND Flash Memory”, IEEE JSAC, 2016 (opened): models each state’s threshold-voltage distribution with a modified Student’s t, whose degrees of freedom set the tail size (many degrees approach a Gaussian, few give a fat tail), with separate values for the left and right tails; its average modeling error is 0.68 percent against 2.64 percent for a Gaussian, and 0.61 percent for a normal-Laplace model. The lab’s option is a simplification: one symmetric Student’s t per programmed state with the state’s mean and standard deviation kept. The erased state is left Gaussian, as with the exponential tail.
Lab values: 12 fresh degrees of freedom, a floor of 3, and a wear gain of 2. No published degrees of freedom were used.

Neutron irradiation (0.20.0)

Chandrashekhar, Puchner, Mitani, Shinozaki, Sardi and Hoffman, “Radiation induced soft errors in 16 nm floating gate SLC NAND flash memory”, Microelectronics Reliability, 2019 (opened): on 16 nm planar SLC parts under neutron irradiation at TRIUMF, the programmed state was more sensitive than the erased state, which was mostly unchanged; the maximum threshold shift observed was 200 mV, of which about 100 mV was the part’s own drift, at a fluence equal to 40,000 years of exposure at New York City sea level; no bit flips were seen. Their stated mechanism: charge generated by the strike leaves holes behind that reduce the threshold of a programmed cell.
Lab choices: a 100 mV shift of the top programmed state, scaled by each state’s level (higher states move more), applied to planar parts only. The scaling by level, and the label “teaching value”, are the lab’s. The 3D charge-trap response is not modeled. Only the shift is modeled, not single-event upsets.

Recovery after an uncorrectable read (0.20.0)

Cai, Ghose, Haratsch, Luo and Mutlu, Proc. IEEE 105(9), 2017 (arXiv 1706.08642, opened), sections 5.2 and 6: neighbor-cell assisted correction extends NAND lifetime by 33 percent (the authors’ SIGMETRICS 2014 paper, not opened); retention failure recovery and read disturb recovery sort cells into prone and resistant by inducing more of the stress and measuring the new voltage, and cut the raw bit error rate of failed pages by 50 percent and 36 percent (their HPCA 2015 retention paper and DSN 2015 read disturb paper, not opened).
The panel is a teaching model of the classification step only: two states, 1,200 cells each, a log-normal spread in how fast each cell moves, a window around the read reference, and an extra dose half the size of the shift already seen. All sizes are teaching values. The percentage the panel prints is the model’s own; the published percentages are shown beside it, never presented as its output. Neighbor-cell assisted correction is quoted, not modeled.

Earlier features

The Gaussian state distributions, wear, retention, read disturb, the ECC ladder, ISPP and the single-trap RTN swing are teaching values from versions 0.1.0 and 0.2.0. They claim no source.