TSMC will host its 18th Open Innovation Platform Ecosystem Forum on September 23, 2026, at the Santa Clara Convention Center. The event, themed ‘Expanding AI with Leadership Ecosystem,’ aims to connect semiconductor designers, technology partners, and customers to discuss how silicon processes, chip packaging, and AI tools are reshaping integrated circuit development. The forum runs from 9 a.m. to 2:30 p.m. Pacific Time and emphasizes collaboration across the foundry, design-software, and IP supply chain.
A14 and A16 design flow methodologies
A central focus of the agenda is next-generation process technology, specifically design flows and methodologies for TSMC’s N2, A16, and A14 nodes. Presentations will address energy efficiency, multiphysics effects, and advanced chip architectures. The forum will also cover updates on tools for established nodes like N3 and forthcoming advanced processes, highlighting the transition from traditional transistor scaling to system-level optimization.
3DFabric portfolio and CoWoS capacity
Advanced packaging receives comparable attention, with sessions dedicated to TSMC’s 3DFabric portfolio. This includes InFO, CoWoS, SoIC, and SoW technologies, as well as TSMC-COUPE. These solutions allow the integration of multiple computing, memory, and connectivity components into three-dimensional systems. This approach is critical for developers seeking higher performance without relying solely on logic scaling, a trend supported by recent reports of TSMC planning to double CoWoS capacity by 2028 to meet AI demand.
Agentic AI in semiconductor design
The forum will also examine the role of agentic AI in semiconductor design, reflecting the broader industry shift toward AI-driven engineering. While TSMC focuses on its ecosystem, competitors are also expanding their advanced packaging and memory partnerships. For instance, OpenAI has deepened cooperation with Samsung for next-generation chip R&D, and SK hynix recently held its Future Forum to define its direction in the AI memory era (TechNews).
Heterogeneous integration as performance driver
The 2026 OIP Forum signals a strategic pivot toward heterogeneous integration and advanced packaging as primary drivers of performance gains. By spotlighting A14 and A16 design flows alongside 3DFabric technologies like CoWoS and SoIC, TSMC is positioning its ecosystem to address the physical limits of transistor scaling. For buyers and planners, this underscores the increasing importance of packaging capacity and design tool maturity. The concurrent expansion of CoWoS capacity and rival advancements in EMIB and HBM supply chains indicate a competitive landscape where system-level integration, rather than just logic node density, will determine AI chip availability and performance.
Technologies Shaping the Next Era of Chips Key
Host published: 2026-09-11T13:00:49+00:00 TSMC’s 2026 OIP Forum to Spotlight the Technologies Shaping the Next Era of Chips Key takeaways ▼ It’s that time of year again. Time certainly flies when AI is chasing you! This year marks the 18th TSMC OIP Ecosystem Forum, and it promises to be bigger and better than ever.
Host published: Thu, 10 Sep 2026 02:10:28 +0000
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