Meta and Panmnesia have proposed a next-generation artificial intelligence (AI) data center architecture designed to make an entire data center operate like a single computing chip. The collaboration, detailed in a Nature Reviews journal, addresses the critical issue that as AI models expand to trillions of parameters, latency increases sharply when relying on conventional interfaces like Ethernet and InfiniBand. By using Compute Express Link (CXL) to connect central processing units (CPUs), accelerators, and memory, the researchers aim to scale the architecture across an entire data center, allowing it to operate predictably as a unified system.
High-fanout switches and optical CXL
The core innovation involves using CXL to reduce variations in latency between racks, a bottleneck that becomes severe as AI models grow larger. To achieve this, Meta and Panmnesia introduced three types of hardware components: high-fanout switches, fabric controllers, and link acceleration units. They also proposed utilizing optical CXL to minimize the physical distance signals must travel. This approach moves beyond traditional network interconnects, treating the entire data center as a cohesive, low-latency computing fabric rather than a collection of isolated racks.
960 connected domains and 90% latency cut
The technology demonstrated significant scaling capabilities, increasing the number of accelerators a single CPU can manage from two to 16, and supporting up to 960 connected domains. Furthermore, the CXL-based technology reportedly reduced latency by as much as 90%, enabling the training of models larger than current AI benchmarks without interruption. Panmnesia CEO Jung Myoungsoo stated that “CXL presents a direction for next-generation AI infrastructure in which a data center operates as a single computing system.” This architectural shift suggests a massive increase in effective computational density and efficiency for future AI infrastructure planning.
Data movement as the new AI bottleneck
This development aligns with a broader industry shift where the bottleneck for AI performance is increasingly identified as data movement rather than raw compute. SK hynix has noted that as AI workloads evolve toward inference and agentic AI, the criteria for system performance are changing, with the location of data and how quickly it moves having a direct impact on efficiency. The Meta and Panmnesia proposal validates the growing importance of high-speed, coherent interconnects like CXL, which are essential for scaling memory and accelerator resources across multiple physical units, making the entire system behave like a single, massive memory pool.
Kioxia GP1 and XL1 CXL modules
The push for higher bandwidth and lower latency in AI infrastructure is also driving innovation in storage and memory technologies. Kioxia recently showcased its GP1 PCIe 6.0 SSD, which is optimized for GPU direct access in AI workloads, delivering up to 10 million random read IOPS. Additionally, Kioxia is exhibiting the XL1 series, a CXL-compatible memory expansion module that uses XL-FLASH to bridge the performance and cost gap between conventional DRAM and SSDs. These developments highlight the industry’s focus on creating specialized storage and memory tiers that can efficiently support the massive data demands of next-generation AI systems.
Phison’s NT$28.3 billion August revenue
The demand for high-performance storage and memory is already reflected in the financial results of key industry players. Phison, a manufacturer of NAND controller chips, reported that its consolidated revenue for August 2026 reached NT$28.276 billion, a 377% increase year-over-year, driven by rapid growth in AI infrastructure and enterprise storage demand. Phison CEO Ken-Cheng Pan noted that AI-driven storage demand remains strong, with PCIe SSD controller chip shipments growing by 77% in August. This momentum underscores the critical role that storage and memory technologies play in enabling the scalable, low-latency architectures proposed by Meta and Panmnesia (TechNews).