TSMC Reportedly Plans to Double CoWoS Capacity to 260,000 WPM by 2028

TSMC is reportedly preparing to double its chip-on-wafer-on-substrate (CoWoS) advanced packaging capacity by 2028, according to a report from Wccftech citing Taiwanese media. The expansion would raise monthly output from an estimated 130,000 wafers per month (WPM) at the end of 2026 to 260,000 WPM by the end of 2028. This significant increase is driven by persistent shortages in AI chip packaging, which have forced customers to seek alternatives from other suppliers.

Arizona campus and AP7 facility expansion

The capacity expansion is expected to focus on TSMC’s Arizona campus in the United States and its AP7 facility in Taiwan. Currently, even though the Arizona site produces advanced logic chips, these wafers must be shipped to Taiwan for packaging because TSMC’s CoWoS capacity is concentrated in the island region. The new Arizona packaging capability aims to reduce this logistical dependency and serve North American AI customers more directly.

Intel EMIB-T capacity estimates for 2028

The shortage of TSMC’s CoWoS technology has created an opening for rival packaging solutions, particularly Intel’s EMIB-T. Analysts cited in the report estimate that Intel’s EMIB-T capacity could reach 15,000 to 20,000 WPM in 2027 and 40,000 to 45,000 WPM in 2028 when converted to 12-inch wafer equivalents. Unlike CoWoS, which uses silicon interposers with through-silicon vias (TSVs) for high bandwidth, EMIB-T uses organic substrate bridges, making it suitable for custom AI chips from companies like Google and Amazon.

Samsung HBM share and Huawei price hikes

This packaging bottleneck is part of a broader supply chain strain affecting high-bandwidth memory (HBM) and AI accelerators. Samsung Electronics is simultaneously expanding its HBM market share, with analysts projecting a rise from 33% in Q2 to 40% in Q4 2026, while mass-producing HBM4 and sampling HBM4E. Concurrently, Huawei has reportedly raised the price of its Ascend 950DT accelerator by up to 50% due to HBM scarcity and export controls, highlighting the financial impact of these supply constraints on end-product pricing (TechNews).

Packaging as a competitive axis for HBM

The reported doubling of TSMC’s CoWoS capacity signals a critical shift in the advanced packaging supply chain, moving from a bottleneck to a competitive expansion phase. For NAND, SSD, and DRAM buyers, this matters because CoWoS is the primary integration point for HBM stacks and AI logic dies. As TSMC scales to 260,000 WPM, the pressure on HBM suppliers like SK hynix and Samsung to maintain yield and volume will intensify. The rise of Intel’s EMIB-T as a viable alternative suggests that packaging is becoming a distinct competitive axis, potentially decoupling memory supply from a single foundry’s packaging capacity.

Geographic shift and procurement strategies

This diversification may stabilize long-term pricing for AI accelerators but requires buyers to qualify multiple packaging ecosystems. The geographic shift of packaging to the US also reduces logistics risk for North American hyperscalers, potentially altering procurement strategies for memory and logic components. As the industry moves toward 2028, the interplay between foundry capacity, memory yield, and packaging architecture will define the cost structure of next-generation AI infrastructure.