Chinese memory manufacturer CXMT is reportedly struggling to achieve viable yields in its High Bandwidth Memory (HBM3E) production, with South Korean media citing a yield rate of only 25%. This figure implies that three out of every four HBM3E stacks produced are defective, a significant setback for a company that has been advancing its memory capabilities. The development places CXMT two generations behind industry leaders like Samsung, SK hynix, and Micron, who are already progressing with HBM4E sampling. For storage and memory readers, this highlights the persistent technical barriers in advanced DRAM packaging, even as demand for high-bandwidth memory continues to surge globally.
TSV immaturity vs 90% planar yield
The core of the issue lies in the immaturity of CXMT’s Through-Silicon Via (TSV) technology, which is critical for stacking DRAM dies. While CXMT reportedly achieves around 30% yields in front-end manufacturing, the back-end processing yield is estimated at about 70% on top of that base. The complexity of TSV integration is significantly higher than planar DRAM manufacturing, an area where CXMT has reportedly excelled with a 90% yield on regular DDR5 production. This disparity suggests that the bottleneck is not in the base die quality but in the advanced packaging and interconnect processes required to create a functional HBM stack.
3,000 TSVs vs SK hynix 8,000
Engineering constraints are further illustrated by the TSV density required for different HBM generations. Samsung uses approximately 5,000 TSVs per layer on HBM2, while SK hynix employs over 8,000 TSVs per layer on HBM3. In contrast, CXMT is reportedly attempting to achieve HBM3E performance with only 3,000 TSVs per layer while packing eight layers in a standard 8-Hi configuration. This lower TSV count may limit bandwidth and reliability, making it unlikely that CXMT will transition to higher-capacity 12-Hi HBM in the near term. The gap in packaging expertise underscores why HBM remains a high-barrier market dominated by established players.
Samsung HBM4 yield ramp precedent
Despite the current low yields, the situation is not necessarily a permanent failure. Samsung reportedly had a 60% yield for HBM4 in February of this year and has since improved to about 80% just six months later, demonstrating that yield ramp-ups can be rapid once the process is stabilized. CXMT’s 90% yield on planar DRAM, which is only 2-3% lower than Samsung’s yield on its 10 nm class node for DDR5, suggests the company has a strong foundation in base die manufacturing. However, mastering TSV stacking requires substantial expertise, and it is expected to take several months before CXMT can commence volume production of HBM3E.
HBM shortage and Huawei price hikes
The yield struggles at CXMT occur against a backdrop of intense global demand for HBM, driven by AI infrastructure expansion. Reports indicate that Chinese AI chip manufacturers are increasingly relying on the gray market to obtain advanced HBM after US export controls tightened in December 2024. This has led to significant price increases, with Huawei’s Ascend 950DT accelerator chip price reportedly rising by up to 50% in two months. The scarcity of reliable HBM supply, exacerbated by yield challenges at emerging manufacturers like CXMT, is directly impacting the cost and availability of AI accelerators in the Chinese market (TechNews).
HBF and Kioxia GP Series alternatives
As HBM supply remains constrained, the industry is also exploring alternative memory architectures to address capacity and cost challenges. SanDisk has introduced the concept of High Bandwidth Flash (HBF), which stacks NAND flash dies to offer massive capacity and potentially surpass HBM in certain large-scale AI inference applications. Similarly, Kioxia’s GP Series SSD, which won ‘Best of Show’ at FMS 2026, is designed to extend HBM with a high-performance flash tier, enabling AI systems to access larger datasets without relying solely on costly in-node HBM. These developments suggest that the memory supply chain is diversifying beyond pure DRAM-based HBM, offering new pathways for AI infrastructure scalability.